Explore projects

Llama's litle QBF solver

Verilog parser and AST for the Llama Logic toolchain

llogic circuit to Verilog translator

Llama's base circuit diagnostic package

Llama's circuit family generator

Llama's automatic circuit fault modeler

Exact and provably minimal digital circuit synthesis from arbitrary component libraries via QBF solving

Llama's logic base package.

Python interface to the Kissat SAT solver, optimized for speed and compactness.

Python bindings for the CaDiCaL SAT solver, offering incremental solving and performance tuning.

Python wrapper for the parallel Lingeling SAT solver, enabling multi-threaded CDCL solving from Python.